Transistor placement algorithm for automatic layout synthesis of CMOS/BiCMOS logic and interface circuits

The emergence of BiCMOS technology as a VLSI technology presents new challenges for CAD support for VLSI design. In particular, tools for layout synthesis that can handle standard cells comprising a mixture of MOS and bipolar devices are demanded. This thesis makes an important contribution towards enhanced CAD support for BiCMOS leaf cell layout. It contains an analysis of the principal characteristics of typical circuits contained in BiCMOS standard cell libraries that are important from a transistor placement point of view. It proposes a detailed formulation for the transistor placement problem in which a transistor placement problem is reduced to a module floorplanning problem. It proposes an efficient algorithm that can find the optimal module placements for small circuits (containing no more than 6 modules) and sub-optimal module placements for bigger circuits. By employing slicing structured floorplans and shape functions, the algorithm allows overlapping in the placement under certain conditions, and is able to enforce a pre-placement constraints by place the module inside the area specified. Finally, the thesis illustrates the performance of the algorithm on three types of circuits including BiCMOS logic, ECL logic, and I/O buffer circuits.