The Bbl Layout Structure And Algorithm Research

As the kernel and foundation of the Information Technology (IT), Integrate Circuit (IC) has been developing rapidly featuring larger and larger integration scale, more miniatunzation, higher performance and reliability. With the continuous development and application of EDA design methodology for VLSI circuit and systems as well as the advent of the Intellectual Property (IP) module technology, foorplanning and placement have become a key section in the process of their physical design. Main objective of foorplanning and placement is to locate each circuit module in a suitable position with an optimal shape and ascertain the position of the pad of the module in order to minimize chip area and length of interconnection among blocks under condition of fulfilling the requirement of placement constraints. Because is the first important step in physical design,its result will affect the final performance of a chip.Physical design is a complex key link of the VLSI design flow. And the placement is the most important step in the link. Most placement problems are NP complete, which can only be solved by some heuristic algorithms. As the rapid increasing of the VLSI integration scale, it becomes urgent to find effective algorithms for solving placement problems, aiming at improving the placement quality and shortening the computation time. To facilitate placement, we desire an efficient, flexible and effective representation which induces a solution structure for placement optimization to model the geometric relationship among modules. Under this background, this dissertation is intended to report some of our research results in solving BBL (Building Block Layout) problems in VLSI circuit physical design.In this dissertation, we give a survey of recent development on non-slicing floorplan representations, e.g., CBL, BSG, Sequence Pair and O-tree ect.but in the solution space size, code between expense, switching time in code and layout aspects and so on have the difference respectively.This dissertation proposes a heuristic algorithm for solving the Very Large Scale Integration (VLSI) block placement problem. This algorithm materializes reasonable arrangement through designing the sequence according to the blocks'priority, utilizes the side circumscription as the supplementation for decreasing the side waste, compares several possible locations of the blocks' layout, and accepts the optimum location which had the highest priority for consequent establishment. Simultaneously this dissertation elaborate a floorplan representation, which uses the resources that receives more limits as far as possible, and then uses the general resources. Generally there are more opportunities to satisfy the match generally to solve the problem.