The Study, Based On The Sequence Of The Ic Layout Layout Algorithm

Layout design or physical design is the most important and time-consuming step of IC design. Due to the complexity of a floorplan, physical design is often divided into a set of stages, such as partition, floorplanning, placement, routing and compaction etc, each of the steps solving a sub-problem. Researches made in the paper focuse on the stages of floorplanninng and placement. Most representations for floorplans were reviewed and compared, and Sequence Pair (SP) was selected and highly ranked, on which studies were made and several evaluation approaches were implemented, in the framework of simulated annealing algorithm. An incremental floorplan algorithm was given which is a general and concise technique and outperforms others. Two popular data structures were also designed, namely BSTree and Pqueue, to speed up the evaluation. A quick generation method and its corresponding algorithm were introduced and validated. The algorithm showed its high performance in running time. It is shown that the solution space size of a P*-admissible representation is (n!)2, with block relations only vertical or horizontal. A multi-head program to display the floorplans efficiently was also developed and employed, which use the Xinerama technology.