Research On Hierarchical Thermal-aware Placement Algorithm Of Integrated Circuits

As the physical design of integrated circuit (IC) is now challenged by the design methodology and thermal optimization orientations, besides that arising from the design complexities in deep submicron technology. In this thesis, to solve the runtime inefficiency and thermal issue in IC layout, we present several novel physical design algorithms based on the hierarchical design concept and divide-and-conquer technique:To reduce the impact of the algorithm efficiency arising from the thermal optimization process for 2D floorplanning, we introduct the power density clustering integrating with the hierarchical layout method to ensure the global optimum of the chip thermal distribution. In local IC floorplanning,we establish a hierarchical thermal model.In order to ensure local optimality,in the layout of the simulated annealing process, we combine a simple analytical thermal model to calculate the border hot spots to guide the movement of the border module to avoid the border hot spots. Test results show that the temperature achieved good control, so that the chip significantly reduced the number of hot spot distribution. With the latest thermal-driven floorplanning tool Hotspot Floorplan comparison our algorithm can reduce the peak temperature in the chip to 3% of cases, the computing speed of about 300 times.A hierarchical 3D floorplanning design flow is proposed in this thesis to scale down the much enlarged solution space in 3D structure. This two-stage approach first partition blocks into different layers, then it generate floorplans on each layer simultaneously. With this method, the solution space of initial 3D floorplanning problem is scaled down to even much smaller than traditional 2D design. A new power density constrained floorplanning algorithm is proposed to enhance the runtime efficiency of traditional thermal-oriented algorithms. Different from other two-stage thermal-driven 3D floorplanning algorithm [1][2], we consider not only the horizontal but also the vertical thermal impacts simultaneously for power constraint map. Experiments show that we finally get minor max on-chip temperature by evening vertical and horizontal areal power density distribution in 3D ICs and compared to the algorithm without considering the vertical power density stack, which can again averagely bring down the maximal temperature by 7%.This thesis is aimed to solve new physical design problems arising from the VISI structure. With hierarchical design flow and divide-and-conquer techniques, the research work is focused on enhancing the solution quality with high runtime efficiency. Its basic idea and techniques can also be utilized in other physical design optimization algorithms.