A special instruction set multiple chip computer for DSP: Architecture and compiler design

The goal of this research is to introduce a systematic methodology to schedule deterministic iterative DSP algorithms onto synchronous multiprocessor DSP systems. A static scheduling framework that is based upon advanced linear integer programming techniques is used to obtain rate, processor, delay, and communication optimal schedules for a given data flow graph. This powerful design environment facilitates optimal scheduling for randomly connected heterogeneous systems with multiple functional units and finite resources. This framework can also be used in the design synthesis of VLSI DSP architectures. To complement the scheduling methodology, a new multiprocessor DSP architecture utilizing multiported register files (MAMPORTs) and a communication oriented instruction set has been designed. This Special Instruction Set Multiple Chip Computer (SIMC) has been designed to provide supercomputing performance for DSP applications using the integer programming methodology developed.