Research On Key Technologies Of Artificial Intelligence(AI) Instruction Set Simulator

With the rapid development of the domestic integrated circuit industry and the continuous improvement of chip complexity,how to ensure the correctness of the developed processor has become an important content in the chip development process.The instruction set simulator(ISS)is an indispensable tool in the stages of chip design,verification,and application.It can simulate the execution result of each instruction on the target processor by establishing a functional model of the target processor.For more complex artificial intelligence(AI)chips,the development of an instruction set simulator with fast simulation speed and high simulation accuracy is helpful to accelerate the exploration and design of chip architecture,and is also of great significance to shorten the chip development cycle and verify the performance of the operating system.Since most of the existing simulators simulate single-core and multi-core processors,they rarely adapt to high-density parallel threads and synchronization of related threads,lack good support for the functional completeness of processors with single instruction multi thread(SIMT)architecture and the functional verification of parallel operators.Therefore,it is very necessary to design an instruction set simulator that is compatible with the SIMT architecture.After in-depth study of various instruction set architectures,combined with functional requirements and development environment,this thesis puts forward a simulation idea of SIMT architecture,and uses System C to establish a system-level functional model of AI chip,which realizes all functional simulation of instructions.Through the simulator,the functional completeness of the instruction set was verified,and the efficiency of chip research and development was improved.The thesis first studies the working principle of the processor and the theory of simulator technology,and compares and analyzes the basic working principles,advantages and disadvantages of the compile-type and interpretative-type simulation strategies that are more common in the industry.Secondly,starting from the functional requirements,instruction set architecture,register type,thread and storage structure of the developed processor,a simulation idea of the SIMT architecture is proposed,and the main framework,hierarchical structure and overall implementation of the simulator are given.Then,according to the overall framework of the simulator,its functions are decomposed,and the details of the underlying workflow of the simulator are analyzed from the perspective of the design ideas and implementation methods of the main sub-function modules of the simulator.Finally,the thesis designed and passed the test case covering all the instructions of the simulator,which verified the functional completeness of the AI instruction set.Successfully run a series of parallel operators to ensure that the AI algorithm runs correctly on the chip,so that it can meet the various needs of AI processor research and development.The instruction set simulator simulates the instruction function of the processor in the form of software,which not only verifies the functional completeness of the instruction set,but also compares the results of the ISS and RTL models through the chip verification platform in the subsequent software and hardware co-verification process to ensure the correctness of the RTL code,which is of great significance to ensure the successful development of the chip.