Design And Implementation Of The Instruction Fetch Unit And Multiple Instruction Flows Extension In The YHFT-Matrix DSP

With the development of VLSI technology, the chip can integrate more and more computing resources. Designing efficient instruction fetching system to ensure instruction supply of amount function units on the chip is an effective way to improve the computation performance of the chip. This paper designs and implements the YHFT-Matrix DSP's instruction fetching system, proposes the instruction shuffling mechanism for irregular DLP, and uses the mechanism to realize multiple instruction flows extension of the YHFT-Matrix DSP. The main work is as follows:Firstly, according to the instruction fetching requirements of the execution pipeline, designed the fetch pipeline and the L1 program Cache. The fetch unit adds four address buffers and realise non-blocking mode, and to alleviate the negative impact of the fetch pipeline influence on the execution pipeline. L1P sets two internal state machines to process the requests from fetch unit and dispatch unit with the highest priority in order to minimize the overhead of packet loss when cross-border dispatching. The fetch unit and L1 program Cache is fully verified and the YHFT-Matrix DSP is synthesized with critical path optimization.Thridly, based on the anlaysis of ineffective causes when developing irregular DLP in traditional SIMD architectures, this paper proposes the instruction shuffling mechanism and the instruction shuffle micro-architecture. The instruction shufflling mechanism provides several different instruction flows to all SIMD lanes, supporting irregular DLP in the SIMD architecture. Response mergering and buffer mergering mechanism further enhance the efficiency of the instruction shuffling mechanism.Finally, based on the instruction shuffling mechanism, multiple instruction flows extension is implemented in the YHFT-Matrix DSP. Using 8 instruction memories with the depth of 256 each, the extension consumes 2.97% area overhead and pushes the program speedup up to 1.59 on average.