| The high cost of capital equipment for production testing coupled with the time that an analog circuit spends on a tester has made it imperative to minimize average chip testing time during production. Testing time can be reduced by decreasing the number of tests that need to be performed on a circuit. This can be done by studying circuit simulation data. In this thesis, a new testing algorithm is presented to break up long tests into many simple measurements and remove redundant measurements. However, generating simulation data for VLSI analog circuits requires an efficient and accurate model to replace time consuming circuit simulation. In order to build accurate nonlinear models for high-dimensional problems, an algorithm has been implemented based on additive regression splines. In some VLSI analog circuits, there is a need to model many performances, each requiring extensive simulation times even for a single simulation. This problem is overcome by decomposing a circuit into several blocks, which are linked together by behavioral models. For the mapping of process and device parameters to those block parameters, a regression model or the proposed additive regression spline method is used. |
