A Study On Analog Integrated Circuit Layout Automation

Driven by the increasing need of incorporation both analog and digital circuits on the same silicon chip, design automation for analog integrated circuits has gained close attention and huge momentum in recent years. Several algorithms for analog VLSI layout automation are proposed in this dissertation. The architecture and workflow of the tool is designed. Experimental results are given to demonstrate the validity and efficiency of the proposed algorithms.In this dissertation, we designed the architecture and the workflow of the analog VLSI layout automation tool. The workflow includes input, stack generation, floorplan, routing and output. For stack generation, we proposed the concept of symmetrical Euler's graph and symmetrical Euler's trail, based on which algorithms for two dimension stack generation is proposed. The generated stacks are 2-axisle symmetric and common-centroid that minimum the mismatch. Algorithms for module merging are proposed, which are essentially independent to any topological representation. Module merging algorithms can exploit the possibility of area sharing during floorplanning, which reduce area occupation and minimum parasites. Since some modules need to be placed along the border of chip, algorithms based on O-tree for solving boundary constrains are proposed. Furthermore, for satisfying the needs of placing some modules along the common bus, algorithms for predefined coordinate align constrains are also presented.