Research On VLSI Technology Of Analog Probability-Processing For Wireless Communication Receivers

In the background of Moore's law going the"post-CMOS"era,the power and reliability of digital integrated circuits are highlighted,which limits the space for improving the performance of digital signal processing technology,so it is very important to develop alternative solutions.By taking advantage of probability characteristics of signal during communication signal processing,analog probability processing(APP)technology combines the characteristics of low power analog devices with probabilistic signal processing algorithms,optimizes the speed and power dissipation performance of the system,has the characteristics of high efficiency,high reliability and low power consumption,and can meet the requirements of future wireless communication system in high signal processing demand and high energy utilization efficiency.In recent years,APP technology has made some progress in the theory of communication signal processing,whose research scope involves channel decoding,novel multiple access,multiuser detection and other fields.However APP still faces some problems in the implementation of signal processor and the system application,and its application has been limited.For example,the APP based communication signal processor lacks the design and verification methods for Very Large Scale integration(VLSI),the APP based low-density parity-check code(LDPC)decoder lacks an efficient implementation method,and the APP based probability receiver lacks the probability path between synchronization and channel decoding.This paper starts the study in three aspects,namely,the design of the basic calculation unit design,the optimization of the basic signal processing module and the modeling of the signal processing system,and forms the verification method of VLSI design for complex APP system.On this basis,this paper explores the design method of structure-aware LDPC decoder based on APP and the method of pseudo-code synchronization based on APP,and finally realizes the"full"probability communication receiver based on direct sequence spread spectrum(DSSS)technologies.Main contributions of this work are presented.1.A novel design and verification method,which is divided into three aspects,namely,unit design,module optimization and system modeling,is proposed for the VLSI implementation of complex APP system.In the basic operation unit,by using the physical properties of MOS transistor,the multiplication unit and memory unit of the APP circuit are designed.The parameter design of MOS transistor is constrained by the inversion coefficient,and the accuracy of the unit is improved by analyzing the mismatch effect.In the basic processing module,the probability gate circuits are built on the Gilbert multiplication,the input constraint conditions of circuit design parameters are proposed,the optimizations are adopted in the circuit structure and layout design.Compared with the traditional probability gate circuit,the relative current error is reduced in the proposed one with the improved power consumption and area utilization.In the signal processing system,the hybrid structure/behavior verification model is established by taking advantage of the diagram structure characteristic of the system and the gate-level unit circuit behavior.This verification model can relate the system performance requirements to the underlying circuit parameter design,can realize the circuit optimization design before the layout,and effectively reduce the circuit design cycle.2.The design and implementation method of the structure-aware LDPC decoder based on APP is proposed.In order to solve the problem that the design complexity of the existing APP decoding chip is too high,this paper proposes the decoding structure-aware LDPC code construction method,and uses the isomorphic sub-graph model of the encoding structure to realize the reusable module of decoding network,which can effectively reduce the workload of the chip layout and wiring.In this paper,by verifying the decoding convergence state by checking the probability,a stopping iteration method for APP decoder is proposed,which can improve decoder throughput and save processing power consumption.In addition,the input/output interfaces for APP decoder are designed,which are completely compatible with the existing digital communication system.Finally,the experimental results show that the decoder prototype,which is fabricated in a0.35-?m CMOS technology,can achieve a throughput higher than 50Mbps with the power consumption of 86.3m W for the decoder core,and can offer a superior 6.3d B coding gain at the bit error rate of 10^-6 when the tested throughput is 5Mbps.The proposed LDPC decoder is suitable for the power-limited applications with moderate throughput and certain coding gains.In this paper,we present an implementation of a(480,240)CMOS analog LDPC decoder,which is the longest implemented code to date using the APP approach.3.A design approach of probability DSSS receiver is presented.In order to solve the problem of the lack of probabilistic signal path,a pseudo-code phase estimation method based on APP technology is proposed.More specifically,the PN code phase probability distribution is computed by using the chip posterior probability from the output of the iterative decoder,the search for the correlation probability peak then completes the PN code capture,and the probability signal is provided for the following APP decoder.This paper designs and realizes the DSSS receiver,which uses the APP technology to perform the baseband probability signal processing including the PN code synchronization and the LDPC decoding.Compared with the digital realization,the APP implementation technology not only has the same reception performance,but also can significantly reduce the number of transistors required to achieve the circuit,and further reduce the communication signal processing power.