| Delay testing, which determines the correctness of operation at the specified speed, is important for modern high-speed digital VLSI circuits. The path-delay fault, in which the propagation delay along a path exceeds a limit, is an accepted fault model for delay testing. This dissertation addresses two important problems associated with the testing of path-delay faults, namely, testing a sufficient set of faults to guarantee correctness, and handling a large number of faults that can grow exponentially with the circuit size.; The first contribution is a novel classification of path-delay faults into three categories: (i) singly-testable (ST), (ii) multiply-testable (MT), and (iii) ST-dependent. Under the single fault assumption, we prove that testing ST faults is sufficient to guarantee correctness and that single-input change tests are sufficient. Under the multiple fault assumption, we prove that testing ST and MT faults is sufficient.; The second contribution is path-delay fault test generation methods. In a deterministic method, tests for ST and MT faults are derived from the conventional stuck-at-fault tests for an equivalent circuit. However, the method is complex. Another efficient simulation-based method, using a novel sixteen-valued algebra, derives single-input change tests for ST faults. Through bit-parallelism and fault concurrency, a seven-fold speedup over the existing methods is achieved.; The third contribution is a fault simulator that handles circuits with exponentially large numbers of path-delay faults. The simulator uses a novel Path-Status Graph (PSG) data structure. It is a dynamically changing circuit connectivity graph containing the detection status of all faults. For the c6288 benchmark circuit, with approximately 10{dollar}sp{lcub}20{rcub}{dollar} paths, previous methods stop due to computer memory limitations after detecting only one million faults. Our simulator continues and reports a coverage three orders of magnitude higher.; In the final contribution, the circuit is resynthesized for testability from its PSG obtained after fault simulation. Many singly untestable path-delay faults are removed using the known stuck-at fault redundancy removal techniques, resulting in an enhancement of single path-delay fault testability. |
