High performance CMOS VLSI circuit design with CVTL

Critical Voltage Transition Logic (CVTL) has a unique speed advantage over other existing logic styles [1] and [2]. As the demand for high speed increases in CMOS VLSI circuit design, CVTL provides a promising speed advantage. The experimental results show that the CVTL inverter chain buffer has a significant speed improvement over that of pseudo-NMOS counterparts. The reported speed-up is 4.5. The basic logic gates and specific circuit applications (e.g., adder) of CVTL are discussed in [3]. The speed improvement of these circuits is significant, but the design is challenging and time consuming. To conquer the difficulty of designing CVTL circuits [3], it is desirable to develop a general purpose platform which can be used to employ the advantage of CVTL family. The Programmable Logic Array (PLA) is commonly used for implementing the complex control logic in microprocessors. For example, a critical piece of the control logic of the Intel Pentium II MMX processor was implemented with a PLA [4]. Recently, many efforts [5] and [6] have been made to improve the performance of PLAs from circuit design point of view and logic synthesis point of view. The general purpose platform chosen for CVTL implementation of general circuits is the PLA.; In chapter 1, an introduction of Programmable Logic Array will be presented first, and then the current primary logic family implementation for designing PLA is given in the second subsection. The advantages and disadvantages of these logic families will also be discussed. The objective of this thesis will be described in the last subsection. In chapter 2, a new logic family is introduced for the PLA circuit design. A comparison among different logic of PLA is presented. A complete complex logic function implementing the new PLA is described in chapter 3. An overall system design flow from netlist generation to layout, circuit extraction, and circuit simulation is presented to verify the performance improvement by illustrating the MCNC benchmark circuit examples. Investigation of the viability of CVTL technology for deep submicron process and low power design is in chapter 4. The CVTL PLA in Finite State Machine application is described in chapter 5. The investigation includes the justification of the circuit speed, power dissipation and signal integration between CVTL logic and flip-flops. The integration of the CVTL technique into static CMOS logic is addressed in chapter 6. The conclusion and future research are discussed in chapter 7.