| This thesis proposes a new theory and methodology for symbolic analysis of analog integrated circuits based on a new canonical representation of symbolic matrix determinants, named Determinant Decision Diagrams (DDDs). DDDs can naturally exploit the sparsity of circuit matrices and the sharing of the product terms of determinants. We present a DDD vertex ordering heuristic, and prove that the heuristic yields an optimum ordering for ladder-structured circuits, and observe that for practical circuits, the number of DDD vertices usually can be orders-of-magnitude less than that of product terms. We show that many DDD operations can be performed in time linear in the number of DDD vertices. By utilizing DDD-graph manipulations, we propose a multi-rooted DDD structure, named s-expanded DDD, to derive s-expanded symbolic expressions. We describe an efficient algorithm to construct an s-expanded DDD from an original DDD. We prove that both the time complexity of the construction algorithm and the size of the resulting s-expanded DDD are OmDDD ) for practical circuits, where |DDD| is the size of the original DDD, m is the highest power of s in the s-expanded expression.;On the basis of the concept of DDDs, we propose a new hierarchical analysis method by performing symbolic suppression of subcircuits and representing their equivalent circuits by DDDs. We address the problem of partitioning a circuit so that hierarchical decomposition uses the minimum number of DDD vertices. We describe an efficient multi-way multi-level partitioning algorithm under balance constraints. Driving interpretable small-signal characteristics of analog circuits by DDD-graph manipulations is investigated. We show that two key algorithms---terms de-cancellation and generation of dominant terms---can be performed elegantly with DDDs. Symbolic circuit noise analysis and modeling are studied and a new method is devised that is able to generate exact noise models for large analog circuits by exploiting s-expanded DDDs. We have implemented all the results in a computer program---SCAD3. As demonstrated on a set of real analog integrated circuits, SCAD3 outperforms existing symbolic analyzers in terms of both circuit sizes and CPU time. |
