A New Hierarchical Method For Symbolic Analog Circuit Simulation

GRASS, (Graph Reduction Analog Symbolic Simulator) analyzes a linearized network topologically. Without partitioning the circuit, the performance of GRASS degrades when the circuit size exceeds certain level. This paper proposes a new circuit partitioning method that takes the advantage of topological analysis framework of GRASS so that the network function of the original network is composed algebraically of the network functions of the partitioned sub-circuits., which are solved by GRASS without running out of memory. Experimental results show that the new method is effective in alleviating the performance bottlenecks in symbolic circuit analysis, the method can be used to handle MOS circuits consist of 117 nodes and 358 elements effectively.