Implementation And Comparison Of BDD-based Hierarchical Approaches To Symbolic Circuit Analysis

Parallel to algebraic methods, graphical methods for symbolic circuitanalysis have the advantage of cancellation-free. This paper proposes agraph reduction method for hierarchical symbolic circuit analysis byapplying a binary decision diagram (BDD) for data sharing. This method isextended from the Graph-Pair Decision Diagram (GPDD) method whichwas developed for two-port dependent sources. New graph constructionrules for multiple-port dependent sources are introduced, with which largeanalog circuits can be analyzed hierarchically. The new hierarchical methodguarantees the cancellation-free property at each layer of hierarchy. TheBDD-based hierarchical analysis method can greatly reduce the analysiscomplexity of the entire circuit, while the software construction and circuitpartition remain easy. The new method is compared to the algebraichierarchical method based on DDD (Determinant Decision Diagram) whichdoes not have the cancellation-free property.