Template-driven parasitic-aware optimization of analog/RF IC layouts

Technology scaling and aggressive electrical performance specifications introduce tremendous challenges in the design and layout of analog and Radio Frequency (RF) circuits. Layout issues such as device matching and symmetry, parasitics, current density in interconnects, and substrate effects are of utmost importance in high performance analog/RF integrated circuits. The complexity involved in modeling these layout-effects for incorporation into layout-automation engines is immense. Thus, traditionally, analog/RF layouts have been crafted manually by expert layout-designers to squeeze-in the desired performance through intricate layout-geometries.; In this dissertation, we present algorithms and methodology for reuse-centric automation of analog/RF layouts that is geared towards technology migration and electrical specification change. Under this scheme, a symbolic structural template is first automatically extracted from an existing analog/RF layout. The symbolic structural template comprises constraints due to design rules, parasitics, symmetry and relative placement of devices and wires. The number of constraints limits the applicability of template-based methods for layout automation to smaller circuits. To this end, a multi-level constraint generation scheme is presented to extract only non-redundant constraints. For limiting the effect of parasitics, constraints on layout geometry are generated by formulating an optimization problem based on the circuit's sensitivity to parasitics. The target layout is then automatically generated from the symbolic structural template by combining mathematical programming with the graph based longest path technique.; A computer-aided design tool called IPRAIL (I&barbelow;ntellectual P&barbelow;roperty R&barbelow;euse-based A&barbelow;nalog/RF I&barbelow;C L&barbelow;ayout) has been implemented incorporating the above techniques. From an existing layout representation, analog/RF circuits are automatically retargeted by IPRAIL to different processes and electrical performances; the corresponding correct-by-construction layouts have performances comparable to manually crafted layouts. While manual re-design and re-layout of analog/RF circuits is known to take weeks to months, IPRAIL achieves comparable performance in minutes to hours.