A Hierarchical Symbolic Simulator For Analog Circuit Design

Highly automatic electronic design tools for analog circuit design are scare due to its great complexity and experience-based design flow. Repeated simulation iterations are usually involved for analog circuit designers to reach the design specification. On the other hand, the advent of SOC design results in an ever enlarging gap between designers'productivity and a shorter time to market requirement. To address this problem, a hierarchical symbolic analysis method is proposed in this paper, aiming to increase the design efficiency with the inherited merits of symbolic analysis.The proposed method combined a topological symbolic approach with its algebraic counterpart on two hierarchies. Circuit regularity was fully utilized. Symbolic stamps of sub-circuits with different structure were constructed and assembled to the top circuit matrix, then solved by an algebraic symbolic solver. The simulator's capability of handling large scale analog circuit was improved greatly due to the hierarchical scheme and a compact data structure.The thesis is organized as follows. A brief introduction is listed in Chapter 1. Algorithm and theory of hierarchical symbolic analysis are described in Chapter 2. Chapter 3 talks about the implementation details of the simulator. Chapter 4 presents the experimental results. Chapter 5 summarizes the paper.