Hot-carrier effects in flash memory devices

This thesis focuses on the hot-carrier effects in Flash Erasable Programmable Read Only Memory (Flash EPROM) devices. The Gate-Induced-Drain-Leakage (GIDL) current during the source-side erase of Flash EPROM generates interface traps and induces a large amount of hole trapping in SiO{dollar}sb2,{dollar} causing many reliability problems. To improve the reliability performance of Flash EPROM, we have introduced a two-step erase algorithm in which a second erase step is used to neutralize the trapped holes generated by the previous source-side erase. We have also discovered a combined disturb effect in Flash EPROM circuits, which points to the necessity of finding the "worst-case" in evaluating the reliability of Flash memory. For better understanding and modeling of the erase-induced damage, it is highly desirable to profile the nonuniform erase-induced damage, which had been a difficult task as the damage is localized near the gate edge. To this end, we have developed a direct lateral profiling technique, based on the charge pumping current measurement, to characterize the nonuniform hot-carrier damage in MOSFET and Flash memory devices. The charge pumping curves are directly transformed into the lateral distributions of junction doping and localized hot-carrier damage. Applying such method to Flash memory devices, we have studied the lateral distributions of the erase-induced damage, including both oxide charge and interface traps. In particular, we have found that both the magnitude and the lateral extent of the erase-induced damage increase with the source-side erase bias, and the peak-damage location shifts towards the channel. With the help of the profiling technique, we have also analyzed the enhanced hot-carrier effects in scaled Flash memory devices. More erase-induced damage is spread into the channel if the erase junction is more abrupt, and the effect of such damage on device {dollar}Vsb{lcub}t{rcub}{dollar} becomes more severe when the effective channel length is scaled down, seriously reducing the operating cycles of Flash memory devices. These results have led us to suggest two approaches to scale down Flash memory devices without sacrificing their reliability: (1) reduce {dollar}Lsb{lcub}eff{rcub},{dollar} keep a graded source junction, and keep the erase bias around 5V; or (2) reduce {dollar}Lsb{lcub}eff{rcub},{dollar} reduce the source junction depth, and reduce the erase bias.