High-performance Low-power Vlsi Architecture And Interconnect Research

The design and implementation of high speed low power VLSI structure and the analysis and design of high performance on-chip interconnect are two key fields of VLSI design.In the first part of this thesis, some low-power techniques in the gate and algorithm level are carrried out. A pipelined multiplier using EMODL logic is implemented and optimized in the gate level for low power comsumpsion. In the image processing field, in this thesis the implementation of 2D IDCT transformation for MPEG 2 using forward-mapping and motion estimation structure for MPEG 4 encoding are proposed. Power optimizations in the system, structure and circuit level realize efficient computation with low power dissipation.In the second part of this thesis, the analytical method to extract interconnect capacitance and the analysis and design of high performance on-chip interconnect are coverd in detail. The capacitance extraction method based on conformal mapping is improved in accurancy, which can be useful to optimize the parameter scanning for interconnect analysis. Based on distributed RC and RLC transient response model, the methodology to optimize overall performance of global wiring in VLSI is proposed. The effective thickness of interlayer dielectric is derived through power and bandwidth optimization, which can be used as an base for process optimization.