Research On The Layout Design Of Encryption SOC

Nowadays System on Chip(SOC) has become a research focus in IC design filedas the development of very large scale integration(VLSI) and new process technology.Generally, it takes a long time to complete a design cycle, including front design,layout design and final tape-out. During the process of layout design, the balance oftiming, power and chip area decides the quality of design, even the success of theproject. Besides, the timing closure in Multi-Mode and Multi-Corner(MCMM) alsobrings challenge to the layout design. It’s significant for commercial SOC to study thephysical design in deep-submicron(DSM), including the balance of design and timingclosure in MCMM.This paper is based on the physical design of a commercial encryption SOC,called HS1308. At first, the paper introduces the general process of the overall designfrom behavioral description to Tape-Out. Then the timing closure of layout design inmulti-Mode and Multi-Corner has been researched. According to the feature ofHS1308, the paper proposes the corresponding MCMM solution project.The design is based on HJTC110nm process. A practical operating andtheoretical research are shown in detail for logic synthesis and layout design of SOCHS1308, using Design Compiler and IC Compiler. Then the design is analyzed andoptimized from design timing, power dissipation, congestion to many other aspects.The results meet the design requirements and the commercial SOC mentioned inpaper has completed Tape-Out successfully.In the finality, the problems requiring further studies are discussed.