Research Of Design For Testability For8bit MCU

The rise of the chip complexity asks more strict requirements on the faults may begenerated by the chip manufacturing and packaging process. Fault tests for theproduction side, before the chip delivery to the customer is one of the essential part. Thetraditional testing method relies on test pattern which is written manually, so theperformance and fault coverage are low. But this method is useful for small-scale,simple structure chip. However, in recent years, with the increasing scale of integratedcircuits, chips are becoming more integrated, already gone from the ten million gatelevel into the hundreds of millions gate level, and has been commercially available. Inearly2008, one processor with billion transistors was available. Manufacturing processcontinues to improve makes20nm product has been commercialized. Electronic designautomation (EDA) tools are constantly improved; large chip such as the system on chip(SOC) becomes popular. Chip integrates with reusable Intellectual property (IP)modules has been widely recognized in the industry and all above makes the complexityof chip rapidly increases. At the same time, the probability of failure in themanufacturing process increases relatively. This makes higher requirements on chiptesting and reliability guarantee. The test cost has accounted for a considerable part ofthe total development cost. The design for testability (DFT) is introduced in order tomeet this demand, by adding additional logic circuit in the chip to control and observe.This method has significant improvements on reducing test difficulty and test cost,improves test efficiency than traditional methods.This article firstly introduces the principle as well as the main method of design fortestability and analyzing the advantages and disadvantages of the regular methods oneby one, different methods correspond to different circuit structure and characteristics.Then based on an8-bit micro control unit (MCU) apply design for testability on digitallogic, analog module and the memory unit, so that improve chip fault coveragecompared to the traditional method and reduce test time1.13s. Finally chip faultcoverage up to91.49%through simulation result, memory fault coverage reached100%.Meet the design specification, but no change in the original logic function. This article apply design for testability on the MCU modules (digital blocks, analog modules, andmemory modules), it also has value of reference for the SOC chip.In the last part, propose the optimized methods for the completed design fortestability, take arithmetic logic unit (ALU) as an example, comparing the differencebetween single scan chain and several scan chains. Taking into account the test vectorslossless compression method, propose reasonable compression scheme. Finally, throughcomparing optimized structure and before, choose the most suitable design applied tothe MCU.