8-bit MCU Design Verification And Test Vector Fault Coverage Analysis

Embedded MCU is playing a more and more important role with the science and technology development. It's widely applied to domains of industry, life and scientific research. From the intelligent system, for example, realization of data acquisition, processes control, fuzzy control and so on, to our life, we cannot but depend on the MCU. Thus the research in MCU has always been a focus of electronic engineers.89-family is produced by ATMEL America. It's a new type MCU and can be compatible with 8051. Because it has Flash memorizer in them-selves, 89-family is widely applied in product research, products of portable merchandises and portable apparatus. Otherwise, 89-family is one type of mainstream single chips which replace MCS-51 family at present. An 8-bit MCU (ssh417 product), which can be compatible with the instruction set of 89 MCU, was analyzed in this paper. Then we did the Functional Verification on it and analyzed the percentage of fault coverage for those test vectors according to design project.There are two directions in test method. 1) Put some measurability structures when designing IC, that is to say the method based on DFT; 2) Traditional method is not base-on DFT. The method of measurability is direction of test technology development. However, for this project of 8-bit MCU, for the reason of its requirements of product and project, if we use the method of measurability, it will make design more difficult, and it will make chip size and cost of production increase at last. Therefore, we extracted industrial test-patterns which are generated by stimulus of function verification in the system. That is to say, the test method is not based on DFT.Stimulus generation and coverage evaluation are cores of verification based on simulation. In this paper, we studied this problem in order to analyze the percentage of fault coverage through Verilog structured netlist directed toward MCU project.First, we built system of simulation environment based on Verilog-HDL, consisted of extracting structured netlist, application of order set compiler, system external logic modeling and writing all kinds of stimulus. Second, we verified the function of structured netlist by using Verilog-XL simulation tool of Cadence Company and analyzed the percentage of fault coverage by using Verifault-XL simulation tool at the same time. Finally, on the base of the statistics file of fault coverage, we analyzed the fault points -"status=undetected". Then, we improved the test programs partially and added some function points of test properly. So the percentage of fault coverage was improved effectively to 92.1%. This study showed that this percentage could satisfy the project requirement of Suzhou National Microelectronics Company of HIT. Then this MCU can be produced and tested for the first time.