| This thesis is devoted to the performance analysis of reconfigurable logic accelerators in heterogeneous multi-core architectures, where the multi-core processors are directly interconnected with reconfigurable logic. A Simics full-system simulation was developed to simulate a reconfigurable logic accelerated multi-core architecture, where the accelerator reconfigurable logic is dynamically reprogrammed to accelerate a variety of operations depending the workload. Focus is on the analysis of the effects dynamically reprogramming a reconfigurable accelerator has on a multi-core system running a dynamically changing workload. The selected workloads perform operations commonly performed in data centers, with focus on telecommunication applications. The analysis shows the benefits and disadvantages of dynamically reprogramming accelerator logic and some of the considerations that need to be made in such an architecture. In the full-system simulation, the dynamic reconfiguration algorithms provided a performance increase of greater than 38% compared to the best static accelerator configuration, and a performance increase of over 57% compared to the runs using only the general-purpose cores. |
