Manycore Processor Architecture With Dynamically Reconfigurable Logic Core

With the evolving of semiconductor technology, the Moore's Law is continuing, and the number of processor cores integrated on single chip goes on increasing. For power and area efficiency, manycore processor architecture is an unescapable choice. With abundant of computing resource and highly efficient on-chip-network, manycore is suitable for applications with throughput requierments. As the processor core integrated on manycore will be finer, the performance of single thread application may diminish while executing on a single core. For this problem, recently, manycore processor with capability of constructing reconfigurable logic core become a remarkable solution, in which several cores (named physical core) are combined as a coarse grain logic core, expecting to efficiently translate transistor resources into performance gaining of sequential programs. There is little research effert is made on communication overhead, logical core flexibility and application mapping for these manycore architecture.Aiming at efficient execution of sequential applications on manycore processor with fine grain cores, in this dissertation, intensive study is carried out on execution model, micro-architecture, and resource tuning, etc, and much academic value is achieved for manycore architecture with dynamically reconfirable logic core. The main content and achievement includes:(1) Proposed manycore processor FTP A (Flexible Tiled Processor Architecture) with dynamically reconfigurable logic core. FTPA takes advantages of dataflow-lile execution model EDGE (Explicit Dataflow Graph Execution) instruction set architecture, and ILP (instruction level parallelism) and TLP (thread level parallelism) are exploited in the way of dataflow execution and fine grain thread level speculative execution while not impacting serial programming model. To overcome the overhead of logic core reconfiguration, In FTPA, the computing resources and shared resources are separated through on-chip network, resulting in resource tuning in two levels and two frequencies, meaning much more flexbility.(2) Designed an estimator of speculative execution capability to direct the logic core dynamic reconfiguration. To achieve reasonable logic core reconfigurtion, based on temporal locality and the observing about execution phases, three estimators of fine grain thread level speculative execution capability are proposed on the conception of speculative execution phase and depth, named local history, global history and tournament estimator. Experiments results show that, the estimator of speculative execution capability is able to predict the trend of concurrency changing accurately in different execution phases, while consuming only tens of bits hardware memory resources.(3) Explored the efficiency of applying the estimator of speculative execution capability on logic core dynamic reconfiguration. For different design constraints and applications styles, the computing resources, including instruction window and function units, are able to form logic core in two ways, flat and deep. The estimator of speculative execution capability is used for logic core grain tuning of FTP A in the two ways and experiments results demonstrate that, with the direction of estimator of speculative execution capability, comparing to fixed grain of logic core, nearly half resources are enough for concurrency exploiting of sequential application, with less than 13% performance diminishing, which means much higher resource utilization ratio.Several conclusions are achieved from the work:(1) Constructing logic core is an efficient way for sequential program execution on manycore, but requires reasonable micro-architecture support, such as splitting of computing and shared resources, flat and deep models of application mapping, etc.(2) Reasonable trade-off between performance and resource utilization must be achieved while sequential program executing on manycore with fine grain thread level speculative. For this purpose, accurate understanding about concurrency variation of application execution must be obtained, and the estimator of thread level speculative execution capability is an attractive attempt.The schemes in this disseratation, such as separation of computing and shared resource, logic core constructing in flat and deep manners and the estimator of speculative execution capability, are able to be expanded as universal techniques.