Hardware Accelerator Engine Design For Key Algorithm In Heterogeneous Multi-Core Systems

With modern digital signal processing (DSP) developing to large volume data, and high speed real-time computing, high speed,high performance computing and their implementation methods become an important proposition of modern mathematics and information processing technology. For the traditional single core processing system is difficult to meet the demands of huge amount of information processing and complex signal processing, multicore chip technology provides effective solution to solve this problem, and has been widely recognized. Especially the heterogeneous multi-core systems which integrate a variety of system structures and functions of different processor cores, can assign different computing tasks to different cores for parallel processing, accelerate the task execution through heterogeneous cells, provide more flexible and efficient processing mechanism for a variety of applications, and satisfy the demands of wider application range,which has become one of the main development directions of the future multi-core technology.With the growing demands of high performance and high density complex calculation, mapping computing task in different processing cores of multi-core systems is difficult to meet the requirements of high-speed and real-time processing. Therefore, multi-core architecture arises at the historic moment, and some multi-core processors integrate customized accelerators to speed up the specific application with low flexibility. With the emergence of reconfigurable technique, applying reconfigurable computing technology to hardware accelerator, can make up for the gap of the general operation and software calculation on the performance and flexibility, and provide higher performance platform for complex high speed signal processing.Aiming at these problems, this thesis studies the related reconfigurable computing and hardware accelerators in heterogeneous multi-core systems.The main work of this paper is as follows.Firstly, this thesis refines for the characteristics of application of high density calculation and some algorithms on the basis of application requirements characteristics, analyzes the calculation types which have high degree of reusability and can effectively improve the system performance, analyzes and optimizes the algorithm of these operation types, and puts forward a new matrix inversion algorithm, function fitting method and new architecture based on algorithm.Secondly, the thesis designs a reconfigurable hardware accelerator engine for heterogeneous multi-core systems on the basis of the optimization algorithm and structure, which can accelerate a variety of arithmetic types. Especially, this hardware accelerator engine is able to efficiently complete the matrix inversion of 16,32,64,128 order in single precision floating-point real format, In addition, in order to enrich the function of the hardware accelerator engine, multi-unary operation and function fitting operation are integrated on it without any increase of computing resource cost.Finally, this thesis carries out a series of experiments to verify the functional correctness and effectiveness of the hardware acceleration engine. Briefly introduces the integration of hardware accelerator engine in heterogeneous multi-core system, and the engine is proved effective.