Study On The Influence Of TSV Thermal Stress On The Static Timing Of The Circuit

With the feature size of modern semiconductors decreasing and the number of interconnects rapidly increasing,the interconnection problem has become the primary problem that restricts the design,manufacturing and performance of two-dimensional integrated circuits.The interconnection crisis has become an important bottleneck which limits the development of integrated circuits.However,the emergence of three-dimensional integration technology has brought an effective solution to the interconnection problem.It has greatly reduced the length of the interconnection line,reduced the power consumption of the circuit,and improved the chip integration.In particular,the vertical interconnection Through-Silicon-Via(TSV)technology has become an important technique in 3D integration.However,the introduction of TSV structure will also bring reliability problems to the circuit,and the thermal stress problem is particularly serious,which has become the focus of research in 3D integrated circuits.In this paper,we have studied the cylindrical TSV structure about its thermal stress distribution and impact.At the meantime,we have analysed the impact on the circuit timing.First,according to the cylindrical TSV structure,the thermal stress generated by TSV has been modeled based on the related theory of mechanics and physics,and the mathematical analysis model of thermal stress has been obtained by solving the boundary conditions.After that,the finite element simulation of TSV structure was carried out in ANSYS and compared with the analytical results to verify the accuracy of the analytical model.Then,according to the established mathematical model of thermal stress,the thermal stress distribution of cylindrical TSV has been calculated.According to the piezoresistive effect,the carrier mobility change under different channel directions has been calculated.The research has shown that when the channel direction of the device is [100],the mobility of carriers varies greatly along the axes.When the channel direction of the device is [110],the change in the area between the coordinate axes is large.After that,the influence of copper radius and thickness of oxide layer on carrier mobility has been investigated.As the copper radius increases,the mobility of electrons and holes changes to a greater extent.On the other hand,as the thickness of the oxide layer increases,the mobility of carriers decreases slightly with little change,due to the fact that the oxide layer can absorb the stress.The effects of two TSVs on the device mobility has also been studied.The changes of device mobility has also been analyzed when the TSVs vary.According to the structure of TSV,its electrical parameters has been extracted,including the equivalent resistance and equivalent capacitance of TSV,and the influence on the delay of the circuit when the radius and length of TSV changed has also been studied.The results show that the larger the copper radius,the greater the circuit delay.The longer the TSV,the greater the circuit delay.We aimed at a 0.25?m CMOS process inverter,studied the impact on inverter's delay time due to the change of different carrier mobility caused by thermal stress.The research shows that the hole has a great influence on the rising delay of the inverter,and has little effect on the falling delay.On the contrary,the electron has a greater effect on the delay of the inverter falling,and has less effect on the rising delay.Then we select a simple clock tree circuit with TSV structure,and the influence on the delay of the circuit is analyzed when the mobility of different carriers changes due to thermal stress.In the case of a consistent degree of mobility variation,holes have a greater effect on the circuit delay than electrons.Finally,we have proposed a simple timing optimization method by adjusting the arrangement of the device,which can eliminate the impact on circuit delay because of the mobility changes caused by TSV thermal stress.