| In recent years, vision systems based on CMOS image sensors have acquired significant ground over those based on charge-coupled devices (CCD) [1–5, 7]. The main advantages of CMOS image sensors are their high level of integration [1], random accessibility [2, 6], and low-voltage, law-power operation [1–3]. Accordingly, they offer system-on-chip capability and allow on-chip image processing with low production costs [1, 3, 7]. For these reasons, they have gained potential for use in many applications, especially where integrated functionalities are advantageous, such as in security, biometrics, and industrial applications [8–11].; Most of the reported designs, however, include these on-chip image-processing functionalities at the expense of silicon area. This can limit the maximum spatial resolution achievable. Here, we overcome this limitation with a straightforward, yet robust, VLSI implementation of numerous on-chip image-processing functionalities using double sampling (DS) techniques. Our method employs two sample-and-hold (S & H) circuits per column to perform parallel sampled-differentiation of the captured image. This technique can be applied in the spatial domain as spatial double sampling (SDS) to carry out edge detection functionality, or in the temporal domain as temporal double sampling (TDS) to perform motion detection functions in an image scene, especially in the linear mode.; Logarithmic image sensors have high optical dynamic; however, they suffer from high fixed pattern noise (FPN) inherent to their operation. Therefore, it is desirable to remove this spatial noise. Unfortunately, the correlated double sampling (CDS) method usually used to remove noise in linear image sensors cannot be applied for FPN removal in logarithmic sensor because of non-existence of a “reset” signal to start with. This motivated us to introduce a novel method for FPN reduction in logarithmic image sensors. This method is based on the so-called modal double sampling (MDS) technique first presented in this thesis. This core of this technique is a tri-mode “super” active pixel sensor (3M-APS) and two S & H circuits. This pixel can work in three modes of operation: linear (Lin-APS), logarithmic (Log-APS), and “reduced compression” logarithmic (2Log-APS) by choosing the proper control signals. |
