A Study Of Design Technology For CMOS Image Sensors With High Performance

This paper is a part of research work on Tianjin technological key project "study of CMOS imaging sensors with large dynamic rang and high performance". The study of design technology of CMOS imaging sensors for applications where both large dynamic range and high frame rate are required is our main work. The new readout circuit for reduction of noise, dual sampling and storing in pixel for dynamic extension and system design are creative.The following are what to be presented in this paper.The development trends of CMOS imagers and the influence of the development of CMOS technology is analyzed. The design technology to improve sensitivity of typical pixel architecture is comparably studied. Both photodiode type pixel and photo-gate pixel are usually adopted, but their sensitivity needs improved. High sensitivity is easily obtained by PPD or TFA technology, but added process steps are demanded.The study of the reduction to temporal noises and fixed pattern noises is then introduced and a new readout circuit is provided. Column readout circuits should have high reduction efficiency to FPN. In order to remove noises such as FPN from pixels and column-wise FPN, a new readout circuit with accurate balancing differential output are provided, which has an instrument amplifier configuration. Differential processing of pixels signal are also useful for the suppression of noises from supply rails, substrate and digital switches.The technology of dynamic range improvement is also studied and a pixel with dual sampling and storing is given. Multiple exposure technique is one of the feasible approaches to extend the dynamic range of CMOS image sensors, but the complication of signal processing with more than two exposures usually degrade the frame rate. High dynamic range as well as high frame rate can be acquired with the technique of dual sampling and storing in pixel level proposed in the paper for both two exposures and images combination are implement in pixels. With the provided pixel architecture, parallel shutter or rolling shutter can be realized. Finally, based on above design technology, a CMOS APS system with high performance is provided, which can be applied in the fields where high speed, large dynamic range and high definition are required. The sample chip has been verified by Chartered 0.35 micrometer mixed CMOS process through Shanghai ICC in March 2004, the digital part has also verified through FPGA, which lay the foundation for next system sample chip.