Research & Design Of The DTC-Assisted Fractional-N All-Digital PLL

All-digital phase-locked loop(ADPLL)is widely used for clock generation,multi-core processors and data recovery system.It has many advantages of strong portability,flexible loop parameters and easy integration.The phase noise in ADPLL is mainly caused by time-to-digital converter(TDC)and oscillator.Therefore,to reduce the phase noise of ADPLL,the structural optimization of TDC and oscillators are deeply studied in this thesis.The main research contents and results are as follows:(1)A third-order noise shaping TDC structure is proposed.First of all,the error-feedback mechanism is adopted to transfer the first-stage quantization error of the TDC to the second-stage for noise shaping.Then the quantization error after the second-stage noise shaping is used as the third-stage input signal.Finally,the digital signal after the third-time noise shaping is used as the output signal of TDC.The simulation results indicate that the TDC structure of the third-order noise-shaping improves its resolution to 1ps,which effectively reduces the phase noise of the overall circuit.(2)A low-noise LC voltage controlled oscillator(VCO)structure is designed.The NMOS cross-coupled pair is used as the active core,which greatly suppresses the effective noise power from the active devices.Only part of the noise current contributes to the phase noise,while the rest of the noise current actually circulates within the active circuit without contributing to phase noise.The simulated output frequency range is from 3.551GHz to 3.592GHz,the phase noise of LC VCO is from-120.83d Bc/Hz to-123.12d Bc/Hz at 1MHz frequency offset(3)A high-resolution digitally controlled oscillator(DCO)is designed.The coarse-tuned 7-bit and fine-tuned 12-bit digital control words are used to change the capacitance value,the range of the DCO output frequency is determined.The frequency resolution of DCO is about 1.43k Hz.The output frequency range from 3.613GHz to 6.061GHz,the phase noise at 1MHz offset is from-115.51d Bc/Hz to-121.06d Bc/Hz.The low-noise ADPLL is designed and fabricated in TSMC 28nm CMOS process.The entire ADPLL consumes 0.76m W under the 0.9V supply voltage.With lock time is less than 35us,output range is from 2.625GHz to 4.130GHz,the phase noise is from-118.16d Bc/Hz to-120.02d Bc/Hz at1MHz frequency offset,while occupying 0.13mm~2.