Time-Mode Reconstruction IIR Filters for Sigma-Delta Phase Modulation Applications

The design of several low-pass IIR time-mode filters for use as reconstruction filters in digital-to-time conversion (DTC) applications is proposed. Previously, such reconstruction filters were implemented using phase-locked loops. The proposed filters are constructed from a simple digital-like structure involving voltage-controlled delay units. The resulting circuits require very small silicon area and consume very little power. A first-order filter design for wideband reconstruction applications was fabricated in a 0.13 mum CMOS process occupying a silicon area of 170 mum x 100 mum and consumes 670 muW. The results prove for the first time that the concept of time-mode filtering is feasible in a CMOS monolithic process. Another design, intended for narrowband sigma-delta phase signal generation applications, is proposed that utilizes similar building blocks but uses a filter topology that is better suited for implementations with transfer functions having low-frequency poles. High-order realizations can be constructed as a cascade of several first-order sections. Such an approach will be demonstrated in the design of a sigma-delta phase-encoding signal-generation scheme.