Research、Design And Realization Of Low Voltage, High Resolution Second Order Sigma-Delta ADC

With the development of multi-media chip technology, more and more analog designs have been focused on how to effectively implement the A/D transferring in audio field, especially refered to the mp3 code and decode circuits in which the A/D is of great importance used as a recording device.Oversampling ADC, especially Sigma-Delta ADCs have been the most commonly used ADCs in audio signal’s A/D transferring. This kind of ADC is based on oversampling and noise-shaping technology and sacrifice speed for resolution. It has greatly reduced the difficulty of analog design. It has many advantages as compared to Nyquist ADCs, like loose demand on the device matching, higher resolution (14bit above) and so on.This paper is focused on the design of a 1.8V, 16bit resolution, 90dBA SNR, second-order sigma-delta oversampling ADC. The design of sigma-delta modulator and the verilog HDL coding of digital filter have been finished. Circuit simulation has also been done. This paper firstly researchs all kinds of sigma-delta ADC, then it uses the designated design specifications to settle the final structure of second-order single bit quantization type. This paper has finished the design of all its subcircuits including integrator, 1bit DAC, comparator and so on. This paper also has some original points as follows. The first one is using matlab sweep method, based on the practical design consideration, to determine all the gain factors in the modulator. The second one is using bandgap voltage as reference instead of directly using the power supply. The third one is the design of a simplified common mode feedback circuit which has effectively avoided the common use of extra voltage source.The last one is the use of clock voltage up-shifting circuit which can change the clock’s high voltage from 1.8V to 3.3V which can effectively reduce the resistor of the NMOS switches, thus could reduce the voltage leakage caused by the switches. At last, the paper has given a detailed structure of the digital filter and has finished the verilog HDL coding. This design uses UMC 0.18um art, input bandwidth is 20Khz, oversampling rate is 128. Practical ADC circuit’s dynamic range is 85dB, signal to noise ratio is 88dBA, total harmonic distortion is -74dB. It has a resolution of 16bit with a layout area of 800um*700um. The static power is 100mw.