| This thesis presents the work on designing and implementing a low power digital baseband core with custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) System-on-Chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of multiple sensors, is designed to control the operation and the interface with the whole MNI SoC based on received downlink commands and store/dump neural data uplink in an energy efficient way. The application specific protocol defines three modes to extract useful neural signals with onchip signal conditioning and discrimination. In Time Stamp Mode, Streaming Mode and Snippet Mode, the core executes basic on-chip spike discrimination and compression, real-time monitoring and segment capturing of neural signals so single spike timing as well as inter-spike timing can be retrieved with high temporal and spatial resolution. To implement the core control logic using sub/near-threshold logic, a novel digital design methodology is proposed which considers INWE (Inverse-Narrow-Width-Effect), RSCE (Reverse-Short-Channel-Effect) and variation comprehensively is proposed to size the transistor width and length accordingly to achieve close-to-optimum digital circuits. Three ultra-low-power cell libraries containing 67 cells including physical cells and decoupling capacitor cells using LVT, HVT and optimum fingers are designed, laid-out, characterized, and abstracted. A robust on-chip sense-amp-less SRAM memory (8X32) for storing neural data is implemented using 8T topology and LVT fingers. The design is validated with silicon tapeout and measurement shows the digital baseband core works at 400mV and 1.28 MHz system clock with an average power consumption of 2.2 &mgr;W. |
