The Design And Implementation Of 5G Baseband Processing Platform Based On Multi-core DSP

The 5th Generation Mobile Communication(5G)network can bring users higher bandwidth rate,lower delay and greater capacity of network connection experience.With the development and updating of 5G protocol standard,baseband processing platform for transmitting and processing baseband signal has attracted more and more attention.As the core component of baseband processing platform,Digital Signal Processor(DSP)can provide a high-performance development environment for mobile communication system software development,which has strong engineering practical significance.The processing platform of " Enhanced Mobile Broadband 5G Terminal Simulator" is studied and developed,including an efficient baseband processing software architecture based on multi-core parallel architecture design,and a realization of the data interaction scheme within multi-core DSP and between chips.The main contents of this thesis are as follows:1.Based on the function definition of 5G terminal simulator,according to the requirement of 5G baseband data processing,two chips of DSP and Field Programmable Gate Array(FPGA)are choosed,and the data interaction requirement of baseband processing board is analyzed and designed.2.According to the architecture of baseband processing platform,in order to model 5G physical layer links and map them to each functional module of baseband processing platform,an efficient software architecture for baseband processing is designed.However,there will be resource competition and inter-core synchronization in the cooperative operation of multiple cores in DSP.In order to effectively avoid inter-core conflicts and improve the utilization of resources in DSP,the mechanism of SYS/BIOS operating system,memory resource allocation and interruption of DSP are studied and designed.By verifying the memory occupancy and correctness of the cell search part in the baseband processing software scheme,the results show that the design scheme is reasonable and feasible.3.In this thesis,Inter-Process Communication Generator Registers(IPCGR),Multi-Core Navigation and Enhanced Direct Memory Access(EDMA3)are designed and validated to achieve synchronization and communication between multiple cores of DSP.The transmission rates of multi-core navigation and EDMA3 can reach 38 Gbps and 40 Gbps respectively,which can meet the needs of no less than 10 Gbps.4.In this thesis,hyperlink,Ethernet and Serial Rapid I/O(SRIO)are designed and validated to realize data interaction between chips in baseband processing platform.The transmission rates of Hyperlink and SRIO communication schemes can reach 16.8Gbps and 12.7Gbps,which can meet the needs of no less than 10 Gbps.The transmission rate of the Ethernet communication scheme is 0.644 Gbps,which achieves 64% of the theoretical communication rate and meets the design requirements of the project.