Delay line based CMOS analog to digital converter

This thesis demonstrates a delay line based digitally intensive CMOS analog to digital converter. Analog to digital conversion is achieved using time to digital conversion of delay cells whose delay is approximately linear with respect to input voltage. Conversion is achieved over a full scale input, ranging from 0V to Vdd, with Vdd as the voltage reference for the ADC. An 8-bit ADC was designed and simulated using IBM 130nm technology and demonstrated to have an INL of less than 3 LSB and a DNL of less than 3 LSB at 1.2V Vdd with a sampling frequency of 200kHz. The ADC was verified as functional with a Vdd of 1.4V as well. The primary benefit of this ADC is that it can be implemented in a purely digital CMOS technology because it is implemented using only standard NMOS and PMOS transistors.