Research And Design Of The ROIC In Analog Domain CMOS-TDI Image Sensors

Line-array image sensor is a special kind of image sensor, which can captureimage information in the form of two dimensions by only one line pixels whichworkes in scanning mode. This special working pattern makes the high resolutionimage capture possible, so the line-array image sensor is especially suitable forapplications in space imaging, medical imaging and industrial monitoring. But theexposure time of the pixel in the line-array image sensor is limited by the relativemoving speed of the sensor, which will degenerate the signal to noise ration (SNR) ofthe sensor, especially in the situation of low illumination and high relative speed. TheSNR of the line-array image sensor can be improved through time-delay-integration(TDI) method, using which the sensor can expose multiple times towards the sameobject and accumulate the multiple exposure results together to improve the SNRbecause the energy of the signal is increasing faster than that of the noise during theaccumulation.This thesis focuses on the key technology in the readout circuit of deepsub-micron CMOS-TDI line image sensor. Especially, the main problems in theCMOS-TDI image sensor design are came up, and the method of exposure, themethod of signal accumulating and the architecture of the image sensor are researchedagainst the problems, and a model is came up based on the researches. Thesynchronization of the same signal capture is guaranteed by the modifiedAlong-Track-Rolling shutter, and the degeneration of the MTF is minimized throughsetting the pitch of the sensing area of the pixel appropriately. A128stages analogaccumulator is designed based on the research of the readout circuit in theCMOS-TDI image sensor which achieves the signal accumulation in analog domain,and the noise characteristic is also analyzed. Based on the research of chip styleCMOS-TDI image sensor, a low power cost digital programmable amplifier whichcan achieve64steps gain controlling with gain range from1to4is designed.Combining the op-amp sharing and dynamic biasing technique, the DPGA canachieved two stages gain controlling of pipelined DPGA through a single op-amp inwhich biasing current is controlled according to the amplitude of output slewing, andthe balance of single op-amp gain bandwidth product between the two stages is alsooptimized. In the condition of5MSPS sampling rate and3.3V supply, the DPGA can achieve12bits resolution and its power consumption is only0.65mW, and its functionis verified by silicon chip.