Research And Design Of Wideband Tunable Analog True-time Delay Circuit

In recent years,with the rapid development of wireless communication systems,the analog true-time delay circuits have been widely used in the wireless communication and optical fiber data transmission systems,eg.microwave imager,radar receiver and equalizer,etc.The analog delay circuit is characteriszed in wide band,compactness,high delay resolution,broad reception range and avoidance of beam squinting.In the application of the wideband phased array beam-forming system,the true-time delay circuit can improve the signal-to-noise ratio(SNR)and the communication capacity.Therefore,the research of the analog true-time delay circuit has the important significance for the wideband wireless communication technology development.The wide-band active delay circuit has been researched thoroughly in this thesis.The circuit adopts the two-order all-pass filter that is composed of the differential active inductor(DAI)and single-transistor amplifer.The group delay on the single-transistor all-pass filter is analyzed,and the design method of using the DAI is proposed,which adopts the transconduct enhancement and negative impedance structures to realize the low inductance and high resonant frequency.The tuneability of the delay circuit is researched and the wideband short-delay active delay circuit with DAI is designed and realized.The short-delay wideband active delay cell is fabricated in 0.18 ?m CMOS process,and the measured results show that the delay range of the wide-band active delay circuit is 6-8.5 ps in the frequency band of 3-12 GHz.The wideband active delay line circuit with delay-locked loop(DLL)as calibrated loop is proposed in this thesis.The circuit is composed of the the active delay line and the calibration loop.Through the series combination of coarse and fine delay lines,the delay range and delay resolution are improved effectively.For improving the anti-interference capacity,the DLL used as calibrated loop is proposed.Based on the modelling and system-behavior simulation for the calibration loop,the influential factors in the jitter of the output signal and transient locked time are analyzed,which can improve the loop performance.The proposed active delay line circuit is fabricated in 0.18 ?m CMOS,and the measured results show that the wideband active delay line has the about 5-ps delay resolution and 95-ps relative delay range in the frequency band of 0.6-4.2 GHz.A wideband passive delay line circuit with the trombone-line structure is proposed in this thesis.The circuit is composd of the passive delay cell and active switch circuit.The passive delay cell adopts the metal interconnection line instead of the passive spiral inductor,which improve the delay precision.The modelling and design of the passive interconnection line are proposed for the its characteristic.The novel switch circuit with the structure of controlling the biasing current is presented to mitigate the impact on the the on-off operation state of switches.The proportional to absolute temperature(PTAT)and size scaled techniques are used to improve gain stability under the different delay states and circumstances.The wideband passive delay line circuit is fabricated in 0.13 ?m SiGe BiCMOS process,and the measured results show that the wideband passive delay line has the about 5-ps delay resolution and 35-ps relative delay range in the frequency band of 14-34 GHz.The establishment of the array delay testment modeling is researched in this thesis.We utilize the delay chip as the element of array signal phase control,design delay chip bonding testment system,and realize the delay control for single-chip delay circit and multi-chip cascaded delay line system,respectively.Through adjusting the switches of delay lines at different channels,it makes the neighbouring output signals have a fixed delay time,which simulates beam-forming signal processing for the incident signals with a certain angle,and the delay line array is verified through the PCB testing.The thesis is focused on the research of the wideband analog delay integrated circuit.The wideband short-delay active delay circuit,the wideband active delay line circuit and the wideband passive delay line circuit have been designed and realized,and the array delay testment modeling for the delay chip is established.The key techniques of the bandwidth enhancement,high delay precision,group delay flatness and delay stability are realized.Through the tapeout and test,the design method of the delay circuit is verified to be feasible,which can supply the technical support for the research of the wideband beamforming array.