Design Of High Precision Analog Varaible Delay Line Integrated Circuit

Since the advent of phased-array antennas,it has been widely used in fields such as radar and communications.In recent years,with the rapid development of information,the requirements of high-performance phased-array antennas are also increasing.Due to the limitation of scanning angle,aperture effect and instantaneous bandwidth,traditional phased-array antennas are difficult to meet the requirements of high-performance applications.Compared with the traditional phase shifter,the non-dispersive variable delay line based on the true-time delay technique(TTD)can effectively offset the influence of the aperture transit time,so that the phased-array antennas can face up to the requirements of wide frequency-band and wide incidence angles.The design achieved a high precision true-time delay line.Based on passive and active delay cell,the design can achieve continuous variable true-time delay line.The whole circuit structure is divided into three parts,including the coarse-tuning circuit,inter-stage matching circuit and fine-tuning circuit.The coarse-tuning circuit is composed of active delay units and an analog path selector circuit.The digital control unit controls the analog path selector to realize the selection of the signal path.The inter-stage matching circuit is used to realize the match of the passive circuits and the active circuits.Based on LC ?-network,passive delay cells with varactor loaded can achieve variable delay.The design can realize a small area,low power,large-scale variable delay,high integration true-time delay line.The design has been achieved in TSMC0.18?m CMOS process.The total chip area with I/O pads is 690 × 900mm2.The simulation results show that continuous relative delay time of the true-time delay line is 91 ps.The total delay time includes the delay time of the 3-stage active delay units and the whole delay time of the passive delay units.Each active delay cell can realize 22ps average delay time,and the fine-tuning can achieve 25ps continuous delay.The overall circuit gain jitter is ± 2.1 dB and the maximum delay jitter is 4.9%over a 0.5-3.1 GHz frequency span.The circuit consumes 25.6mW from a 1.8V supply voltage.