Low-power FinFET Circuit Design and Synthesis under Spatial and Temporal Variations

In this thesis, we first propose a methodology for low-power FinFET based circuit synthesis which uses multiple supply and threshold voltages. The scheme is quite different from the conventional multiply supply voltage methods that target power optimization. We also propose a low-power FinFET based circuit synthesis methodology based on channel orientation optimization. We investigate various logic design styles that depend on different channel orientations.;Though FinFETs are a promising alternative to conventional transistors, they are still likely to suffer from the effects of process variations. Process variation can be either environmental or lithographic in nature. Environmental variations can be attributed to both spatial and temporal changes to temperatures and supply voltages in a chip. Lithographic variations results from an aberration in the optical lens used to create the mask in the fabrication process. They are manifested both as systematic and random variations in chip parameters, such as gate length, gate-oxide thickness, fin thickness, etc. Thus, it is imperative to study the effects of process variation on important FinFET circuit metrics, such as delay and power.;In this thesis, we study the effects of lithographic variations on FinFET leakage power. We investigate the leakage power of various standard cells under process variations in gate length and fin thickness. Further, we propose a methodology to analyze leakage power of the full chip under process variations, as well as for a leakage power variation-aware low-power FinFET circuit synthesis. We also perform a statistical delay characterization of FinFET standard cells under both environmental and lithographic variations. We use a central composite rotatable design under the response surface methodology to characterize the delay of various standard cells under varying lithographic and environmental parameter values. (Abstract shortened by UMI.).