| This document describes a novel cell-level analog synthesis solution that can size and bias a given circuit topology subject to a set of performance objectives and a manufacturing process. This technology addresses a critical need in the design of mixed-signal SoC products where time-to-market is the most critical factor to product profitability. To manage complexity and time-to-market, SoC designs require a high level of automation and reuse. The digital portion of these designs can be tackled with one of the ubiquitous cell-based synthesis, mapping, place and route methodologies. These cell-based techniques lend themselves well to a variety of strategies for capture and reuse of digital intellectual property (IP). However, they are inapplicable to analog IP, which relies on tight control of low-level device and circuit properties that vary widely across manufacturing processes. This analog synthesis solution automates these tedious, technology specific aspects of analog design. Thus, it is an essential cornerstone of the next new mixed-signal design methodology that will allow companies to create portfolios of reusable, retargetable, analog intellectual property that can be deployed in time-to-market critical products.; A significant amount of research has been devoted to cell-level analog synthesis. However, this methodology offers a unique combination of features. First, it offers superior accuracy by utilizing the simulation methods used by designers to validate manual circuit designs during the synthesis process. In addition, the formulation allows greater generality and easy of use. To bias and size an arbitrary analog cell the designer only has to specify the topology, reasonable numerical search ranges for each of the independent variables, and the desired perforrnance specifications. Finally, the optimization formulation is robust, producing results comparable to expert manual design. These results are produced in a reasonable amount of time without any additional large infrastructure expenditures.; In addition to describing all pertinent aspects of this formulation, this document presents a set of benchmark circuits and the simulation modules, referred to as evaluators, necessary to characterize them. These results are used as a vehicle to show that, with a minimal amount of effort, it is possible to create a configurable general purpose set of evaluators that are both topology and technology independent. Thus, one can envision a dialog driven user interface that allows the designer to instantiate and configure each desired evaluator. This is a natural extension of the schematic annotations already created by designers on a daily basis and does not require any programming background. Also, based on the benchmark circuits, this document presents a set of numerical experiments that compare and contrast a number of optimizer configurations to highlight the set of algorithms and configuration settings that maximize the robustness and minimize the run-time of this formulation. |
