Research On Dual Threshold FinFET Low Power Combinational Circuit

Energy conservation and comprehensive utilization of resources is an important task for long-term development.Nowadays,information technology is widely used.The power consumption of IC chips is an important source of energy consumption for all kinds of electronic information products.With the integrated circuit technology entering 32 nm and below,the dynamic power density of the circuit is increasing in proportion,and the leakage current is increased exponentially,and the restriction factors such as packaging technology make it possible to for a chip be integrated more transistors.In fact,because of the power limitation,the increased transistors can not work at the same time.Therefore,reducing the power consumption of IC chips is not only of great economic and technological significance,but also will produce significant social benefits.The traditional planar CMOS technology size is set according to Moore's law to meet people's demand for high speed and low power consumption.But in recent years,when the feature size of the device is reduced to less than 32 nm,the reduction of the plane CMOS size is restricted due to the technological factors,and the increasing leakage current Driven by economic factors,the industry tries to develop a variety of new processes in order to continue to reduce the process size,in which the fin type 3-D field effect transistor FinFET(Fin Field-Effect Transistor)is compatible with CMOS and has better performance(smaller sub threshold and gate leakage current,close to the ideal subthreshold slope).And greater conduction current)has successfully become a new mainstream technology for replacing planar silicon CMOS.Based on the FinFET device and the basic combinatorial gate circuit,a new dual threshold FinFET combinational circuit based on the FinFET independent gate and the same gate two structures is proposed in this paper.The static complementary circuit,differential graded switching logic DCVSL(differential cascade voltage switch logic)and full adder circuit are mainly studied.At the same time,the FinFET complementary logic circuit of the independent gate and the same gate structure is analyzed.Finally,a full adder is taken as an example to verify the superiority of this hybrid architecture using the dual threshold FinFET structure.This paper mainly studies the following aspects:1.introduces the structural features and performance of FinFET devices.The advantages of FinFET transistors compared to ordinary CMOS transistors are analyzed.The classification of independent grids and the same grids and their respective performance advantages are studied.2.the influence of various physical parameters of FinFET devices on device performance is studied.The basic combinational circuit is used to study the effects of the number of fins and the power supply voltage on the performance of the dual threshold FinFET device.In order to find the optimal combination of physical parameters.3.a new dual threshold FinFET device is proposed to restructure the symmetric complementary logic circuit and differential voltage switch logic circuit.At the same time,the performance of the two circuits is simulated and analyzed.4.we study the advantages of the new architecture in combinational logic.Finally,we take the full adder circuit as an example to verify the dual structure advantage of the dual threshold FinFET device.Hspice software is used in the simulation of circuit performance in this paper,and the experimental method is to optimize the device simulation through HSPICE.Then the device adopts an optimized dual threshold independent gate FinFET device based on BSIMIMG102.6 model to design a new combinatorial circuit.At last,the simulation results show that the maximum decrease of the delay is 63% with DCVSL as an example.Compared with the same gate,the maximum loss of power consumption is 20%,and the maximum power delay product of the integrated circuit index is optimized by 63%.