| This dissertation presents a high-level synthesis framework for generation of low power and high performance hardware designs from a high-level description language, C. Abstract syntax trees are generated from C descriptions by the SUIF front-end compiler. Then control and data flow graphs are constructed, and control and data flow analyses are performed. Basic scheduling and resource allocation algorithms are applied to generate synthesizable RTL VHDL and Verilog codes. SystemC codes are also automatically generated from CDFG to facilitate hardware/software co-simulation. Power and performance optimizations show the feasibility and efficiency of the synthesis framework.; We present integrated power estimation and optimization methodology in the early stages of behavioral synthesis for unscheduled data-dominated systems, such as digital signal, image, and video processing. Leakage and dynamic power consumptions for module libraries are estimated based on a mixed-level power estimation model with novel switching tables and input pattern tables. An integer linear programming approach is described to explore the switching activities and input data statistics to optimize both dynamic power and leakage power consumption. It performs concurrent module selection, scheduling and resource allocation. The formulation integrates dual threshold voltage technology libraries to reduce leakage power consumption further. In addition, we present a heuristic algorithm based on maximum weight independent set problem to optimize leakage power consumption with dual threshold voltage technology libraries under timing constraints and resource sharing constraints. |
