Design of multi-GHz resonant global clock distributions

The global clock on a microprocessor has traditionally been distributed using a tree-driven grid. Ensuring that this large global network distributes the clock with low-skew and low-jitter in the presence of process, voltage, and temperature (PVT) variation is a significant challenge. With global clock latency on high-performance multi-GHz designs approaching four to five cycles, a skew and jitter budget of 10% of cycle time translates into a delay variation of no more than 2% across PVT corners, a realistically unachievable target.; In this thesis, two new clock distribution schemes based on resonating the clock capacitance with on-chip inductance are proposed and test chip measurement results from prototyped designs are presented. When compared to conventional clock distributions found on high-performance microprocessors today, the proposed schemes achieve measured clock arrival time uncertainty and power dissipation that are improved by almost an order of magnitude.; The first resonant clocking scheme to be presented is a resonant-load global clock. The idea is to augment a traditional tree-driven grid global clock distribution with a set of on-chip spiral inductors. The resulting distribution delivers a uniform phase, uniform-amplitude resonant clock that allows straightforward scalability to different clock load capacitances and different operating frequencies. The second resonant clocking scheme to be presented is a distributed differential oscillator (DDO) global clock. Like the resonant-load clock, the DDO clock resonates the clock capacitance with on-chip spiral inductors. However, the DDO design improves on the resonant-load design by distributing the clock differentially, reducing PVT-induced timing uncertainty at the local clock buffers through differential detection. This is particularly important given the sinusoidal global clock (rather than square wave) that are characteristic of resonant distributions. The design also has improved immunity to PVT variation due to the phase averaging effect of the distributed oscillator topology.