Research On A High Speed Low Noise Low Power CMOS Image Sensor With Pipeline Pixel Operation

CMOS image sensors have replaced CCD image sensors in most applications due to their high level of integration,fast speed,low power consumption and low cost.Compared with the charge transfer method of CCD,the pixel output of the CMOS image sensor is transferred to the readout circuit in the form of voltage,which needs shorter time and is more conducive to high-speed imaging.In addition,CMOS image sensors also allow the design and implementation of more complex on-chip circuits,such as high-speed analog front-end readout circuits,analog-to-digital conversion circuits,and high-speed data interfaces.This makes CMOS image sensors show significant advantages in the field of high-speed,low-noise and low-power imaging applicaitons.With the development of the CMOS image sensor manufacturing process and the improvement of the circuit designs,CMOS image sensor has gradually surpassed CCD image sensor in aspects of read noise,dark current and image uniformity,etc.In this dissertation,we first proposed a pixel array operation method for CMOS image sensors,which pipelines pixel row operations to increase the speed of the sensor.By simultaneously manipulating the pixel control timing of two or more adjacent rows,the frame rate limitation of the sensor caused by the delay of the pixel array control signal line can be greatly alleviated.In aspects of pixel exposure control,an exposure digital state machine is introduced,which reduces the exposure operation time from hundreds of nanoseconds to tens of nanoseconds.In order to verify the proposed method,this dissertation modeled a pixel array.The simulation results show that through the pipelined pixel operation,the peak-to-peak uniformity difference of the pixel array can be reduced from 25 m V to less than 4m V.Based on the proposed pipelined pixel array operation method,we designed an analog front-end readout circuit,and analyzed its noise performance under the pipelined pixel operation.Under high gain conditions,compared to traditional pixel operation,the proposed pipelined pixel operation and front-end readout circuit only add extra 30 u V input referred noise.Secondly,based on a dual-slope ADC with a low-power counting method,this dissertation proposes a low-power ADC structure with column-level oscillators to generate high-frequency counting clocks.For slope ADCs,the transmission and driving of the high-frequency count clock consumes a lot of power.The column-level oscillators can locally generate high-frequency clocks,which saves high-frequency clock transmission power consumption.The column-level oscillator is only turned on in advance when needed.All design and post-simulation of the proposed column-level low-power ADC are carried out.The post-simulation results show that the ADC structure can effectively reduce power consumption.Under 10-bit ADC depth and 1.4us conversion time,the DNL is +0.55/-0.41,INL is +1.63/-1.2,and the power consumption of a single column ADC is only 14.1u W.This dissertation also studied the pixel noise filtering method.Detailed mathematical analysis has carried out on bandwidth limitation,correlated double sampling,and correlated multiple sampling.The effect of correlated multiple sampling times and sampling interval on noise is studied.At the same time,an adaptive filtering method on random telegraph signal(RTS)noise is proposed.By firstly judging the noise of the pixel,then automatically selecting the average filter or the max/min filter,the random telegraph noise of the pixel can be greatly reduced.For the RTS noise filtering algorithm,the measurement results show that after using the proposed algorithm,the number of pixels with RTS noise above 7DN is reduced by about 68%.Finally,a test chip with 180 nm CMOS image sensor process is designed.The pixel array size is 21.45 mm x 21.45 mm and the pixel structure of 4T.The pipeline pixel operation,exposure state machine control,analog front-end readout circuit and RTS noise filtering algorithm proposed in this dissertation are measured based on the test chip.By utilizing the pipelined pixel operation method,the pixel control signal and pixel output signal can be settled under 1.25 us line time,and the readout noise of 2electrons can be achieved.