| In deep sub-micron technology, leakage power consumption has become a major concern in VLSI circuits, especially for SRAM, which is used to build the cache in System-on-Chip (SOC). In this paper, a low power 8-T SRAM cell, based on carbon nanotube field effect transistor (CNFET), is proposed to circumvent the leakage power issue. Experiment datas show that the proposed SRAM cell can save 97.94% static power consumption compared to existing 6T CNFET SRAM cell. In case of writing, the proposed SRAM cell consumes 39.27% less power than the traditional SRAM cell for writing 0 and 58.79% less for writing 1. Also, because of the adoption of a colaborated voltage sense amplifier and independent read component, our 8T SRAM shows much improved delay performance, the delay is observed to reduce by approximate 30% in write operation and approximate 90% in read operation. |
