Research Of Ternary Memory Based On CNFET

Static Random Access Memory(SRAM)is an important part of the digital system,and often used cache for the processor in order to improve the speed of digital systems.Reducing memory access time and increasing storage density is an important indicator of SRAM design.Compared with the SRAM based on binary logic,multi-valued logic breaks the constraint of binary logic signal value "0","1".Such as the minimum cardinal logic in multi-valued logic is three-valued logic,the signal can be "0" "1" and "2".So the multi-valued logic circuit has high density information carrying on single-line and sufficient space or time utilization,it reduces the chip wiring area effectively and improves the SRAM storage density.The traditional SRAM is designed using CMOS technology.As the feature size is reduced to the nanometer level,the gate delay and the crosstalk of the interconnection caused by the parasitic effect of the interconnection line are becoming more and more serious,so that reducing the access time of the SRAM is a great challenge.The carbon nanotube(CNT)has the potential to replace the CMOS process,because it has one-dimensional nature and characteristics of ballistic transmission,stable chemical properties and convenient gate voltage control.Carbon Nanotube Field Effect Transistor(CNFET)can be fabricated using CNTs as channels.Because the gate capacitance of the CNFET is only 4% of the MOSFET gate capacitance,the ternary SRAM designed with CNFET has a smaller read and write delay,which shortens the access time of the SRAM.In the field of information security,the SRAM-PUF circuit can enhance the security of the information system because the physical unclonable functions(PUF)circuit designed with SRAM has better randomness and uniqueness.The main contents of the thesis are as follows:1、Design of single-port ternary SRAM cell based on CNFET: The structure and physical characteristics of Carbon Nanotube Field Effect Transistor are analyzed.The simulation results show that the circuit delay based on CNFET is small and the power consumption is low.Combining the multi-value storage principle and the physical characteristics of CNFET,a single-port ternary SRAM cell based on CNFET is designed.2、Design of high efficiency ternary address decoder based on CNFET: By analyzing the working principle of the address decoder,the ternary basic gate circuit of the address decoder is designed by using the ternary inverter.A ternary high efficiency address decoder with an enable terminal is designed combining the ternary inverter with the ternary basic gate circuit.The decoding efficiency is(1.5)ntimes compare with traditional address decoder.3、Design of high-speed and low-power ternary sense amplifier based on CNFET: In order to improve the read and write speed of the ternary SRAM cell,a high-speed and low-power ternary sense amplifier based on CNFET is designed by analyzing the sense amplifier and the ternary SRAM principle.The ternary sense amplifier can increase the value of ternary SRAM bit line output swing to speed up the read and write speed.4、High performance ternary SRAM-PUF circuit based on CNFET: Using the random process variation generated by the CNFET during the manufacturing process,the cross-coupled ternary inverters generate different precharge current.Combined with the principle of PUF circuit,through the competition of ternary SRAM,generating unique and unpredictable output response,to design ternary SRAM-PUF circuit.The SRAM circuit and the SRAM-PUF circuit are simulated by HSPICE.The circuit logic function,working delay and power consumption are analyzed to verify the high speed and low power consumption of the ternary SRAM circuit.