Analog Neural Classifiers for Built-In Self-Test of Analog/RF Circuits

The seemingly ever-increasing data rates and complexity of modern RF integrated circuits (IC) intensify the test effort that must be spent to guarantee the correct functioning of each manufactured part. Hundreds of sequential tests are carried out in practice using sophisticated test equipment, which creates a major bottleneck in the manufacturing throughput, thereby escalating significantly the overall manufacturing cost. On the other hand, the lifetime degradation of RF devices may result in a gradual decline of their performance or an abrupt failure, the consequences of which may become detrimental for life- and safety-critical systems. A recently proposed machine learning-based Built-In Self-Test (BIST) offers a promising solution to the mentioned problems. A BIST-enabled IC will examine its own functional health using exclusively on-chip resources. The benefits of this feature are twofold. First, in post-production test, it avoids the use of expensive test equipment and eliminates lengthy test times reducing the overall cost. Second, BIST empowers ICs with self-test capabilities after their deployment in the field of operation.;This thesis investigates the prospects and challenges of applying a machine learning-based approach to implementing a fully stand-alone BIST for analog and RF circuits. At the heart of this approach lies an on-chip neural classifier which acquires measurements thought low-cost sensors and makes a pass/fail decision regarding the functionality of a circuit-under-test. Successful integration of such classifier into the BIST architecture hinges on the ability to meet strict area and power constraints of the circuits dedicated to the neural classifier without, however, compromising its ability to learn fast and retain its functionality throughout its lifecycle. Towards addressing these and other constrains imposed by BIST, we fabricated several experimental platforms consisting of programmable arrays of synapse and neuron circuits, developed strategies to train them and evaluated their performance on real data from BIST applications. Our first implementation featured an analog design with digital weight storage and served as a proof-of-concept for demonstrating the network's learning ability for a variety of BIST-related tasks. The subsequent versions targeted the cost-efficiency by incorporating the floating gate transistor technology for non-volatile weight storage, dynamic capacitors for short-term weight storage during training and by employing low-power circuit techniques for energy efficiency. Effectiveness of the implemented neural classifiers in accurately generating pass/fail labels was evaluated using simulation and production test data from several IC designs, demonstrating performance on par with the state-of-the-art off-chip software classifiers.