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Lab-on-a-Chip design automation

Posted on:2007-06-22Degree:Ph.DType:Thesis
University:Carnegie Mellon UniversityCandidate:Pfeiffer, Anton JosephFull Text:PDF
GTID:2458390005481285Subject:Engineering
Abstract/Summary:
A Lab-on-a-Chip (LoC) is essentially a miniaturized microchip implementation of an analytical chemistry laboratory. LoC's that are fast, accurate, automatable and inexpensive to fabricate have been used in the life-science and biomedical industries for applications in genomics, drug discovery, point-of-care analysis and in-vivo diagnostics. Microscale unit operations such as mixing, reaction and separation have been constructed entirely on-chip. In this thesis we present a model-based methodology for automatically designing complex LoC channel systems using large-scale optimization and computer-aided design techniques.; LoC design combines complex physiochemical phenomena with challenging chip layout and channel interconnectivity issues. The chemistry that takes place during chip operation, as well as the chip layout and manufacturing process must be understood so that the appropriate design trade-offs and constraints are considered. Channel geometry, and the system's channel topology have been shown to contribute a great deal to the overall performance of the final LoC design [1]. These issues result in a design problem that is highly nonlinear and highly combinatorial.; Currently, most LoC design involves time consuming laboratory experiments or iterative simulation using computational fluid dynamics (CFD) or finite element modeling packages [2]. While these approaches are excellent for design verification, they are inefficient for design optimization. Reduced order system simulation approaches have been developed, but these methods rely on black-box simulators that are difficult to automate. Some simple shortcut methods for specific LoC unit operations have been presented, however, they lack the generality required for complete system level LoC design. Here we develop the tools necessary to reduce the LoC design cycle from months to only minutes. This thesis covers five major topics: (1) The physical analysis and conceptualization of chip-based unit operations is described in chapters 2 and 3. In these chapters we show how to decompose LoCs into a library of canonical subsystems that share an interconnection interface [3, 4]. (2) In chapter 3, we describe our efficient reduced-order system simulation framework that combines Kirchoffian network analysis and topological sorting from electrical circuit simulation with stream tearing and the sequential-modular structure of process flowsheet simulation [5]. (3) The creation of single and multi-objective nonlinear programming formulations for the optimal design of LoC subsystems [4, 6] and multifunction LoCs is described in chapters 4, 5 and 7. (4) The development of a rigorous General Disjunctive Programming (GDP) [7] formulation for the optimal design of multiplexed LoCs, as well as a more tractable combinatorial formulation [8] is discussed in chapter 6. (5) Efficient tailored solution algorithms to solve our single subsystem formulations are describe in chapter 4 [4]. In chapter 6, Very Large Scale Integration (VLSI) circuit design, iterative heuristics and traditional optimal design techniques are adapted to design complex LoCs [8].; We demonstrate our methodology by automatically designing both single system and multiplexed capillary electrophoresis LoC's. We also address the simulation and optimization of multifunction LoCs that incorporate mixing, reaction, injection and separation processes. We design and optimize an LoC based immunoassay to demonstrate this work. We compare our designs to experimental designs from the literature and designs generated using CFD tools. Finally, we conclude by proposing critical areas for future research and development in this field.
Keywords/Search Tags:Loc, Chip
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