Power consumption in FPGA based bit-serial and bit-parallel digital filter systems

The quest for reductions in power consumption is at the forefront of design challenges in the continuing development of the Integrated Circuit (IC). Power consumption is investigated in digital filters based on bit-serial and bit-parallel arithmetic implemented on Field Programmable Gate Arrays (FPGA). Bit-serial arithmetic is a time-multiplexed version of bit-parallel arithmetic that reuses smaller hardware resources over time. In theory, the same computation on the same platform at the same sample rate using two arithmetic types should not change power consumption. However, the bit-serial and bit-parallel arithmetic map to different fixed FPGA internal hardware resources. This changes the capacitance and switching activity of bit-serial and bit-parallel systems resulting in different power consumptions for operations with same external Input/Output (I/O) behavior. Power consumption changes in a bit-serial and bit-parallel digital filter with respect to implementation changes in arithmetic precision is determined. This allows the choice of the lower cost arithmetic type for an Infinite Impulse Response (IIR) multi-band equalizer based on the required System Word Length (SWL and multiplier Coefficient Word Length (CWL). Power consumption is also investigated for bit-serial and bit-parallel systems between (1) implementations using multiplication by constant and variable coefficients, (2) a Finite Impulse Response (FIR) low-pass filter and an IIR multi-band equalizer, and (3) FPGAs sorted into different classes based on manufacturing process variations in logic timing.