An improved crosstalk noise model for on-chip interconnects

With advances in VLSI and increasing wire densities, crosstalk noise has become the main source of performance degradation. SPICE simulators are not time-efficient estimators of crosstalk; hence alternatives are needed to ensure signal integrity in a limited design cycle.;This study addresses the deficiencies in earlier models and offers an improved multiline model that can be used in design automation. In this model, exponential functions represent switching aggressors rather than step and ramp inputs since it resembles real world signals. The use of dominant pole approximation is also reduced to increase accuracy.;By including the resistive shielding effect, one can formulate equivalent capacitances for tree branches and passive aggressors noting exponential aggressor waveform. A general noise model with many active and passive aggressors is also derived. Results show an average error of 7.98% for noise peak and 9.63% for width with respect to HSPICE while allowing fast analysis.