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Research On Interconnection Crosstalk Noise For VLSI Design

Posted on:2010-09-25Degree:DoctorType:Dissertation
Country:ChinaCandidate:X X LiuFull Text:PDF
GTID:1118360275477248Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
With the increasing scale and complexity of integrated circuits in deep submicron technology,conventional logic-centric design flow has fallen behind the concurrent VLSI design requirements.When integrated circuit process technology approached and went beyond 180nm,interconnection has become a determining factor to the circuit's overall function and performance,thus improved design flows are necessitated.Simultaneously,with the continuous scaling of technology the spacing between wires is getting smaller,while the aspect ratio of wires is continuing to increase.As a result the coupling capacitance between adjacent wires is a dominant component of the total wire capacitance.The capacitive crosstalk noise caused by coupling interconnects may pose a serious threat to the reliability of nanometer design.The interconnection crosstalk noise problem has become the main bottleneck to restrict the sustainable development of VLSI design.Combined with the trend of VLSI design,the main focus of this thesis is the issues related to interconnection crosstalk noise.The contributions of the thesis are as follows.First of all,for the impacts of interconnection crosstalk noise on the circuit function a functional noise failure analysis method is proposed based on the improved noise window model.The transition directions of neighboring nets are injected to the noise window model and an improved noise window model is created. Based on the improved noise window model the noise cluster is analyzed.The timed virtual aggressor is applied to represent the combination result of insignificant aggressors,thus the insignificant aggressors set,the significant aggressors set and the propagated glitch are simultaneously considered.The more accurate realizable effective noise glitch results and the corresponding effective aggressor sets can be obtained.Secondly,for the hierarchical VLSI design two methods are proposed to identify the global false coupling interactions generated by connections between modules.First the definition of logically sensitizable interaction is given.Then the notions of local false coupling interaction and global false coupling interaction are injected to hierarchical circuits.The CIVS(Control Input Vector Set) or X-function is applied to analyze the logic relations of signals in each module,thus the global false coupling interactions of interconnections in hierarchical structures can be identified.Thirdly,for the impacts of interconnection crosstalk noise on the circuit performance a top-k delay noise failure analysis method is proposed.Because of the too huge interconnection analysis space,the logic relations are considered to effectively prune the analysis space of victim line and aggressor lines.Then the occurrence probability of the false delay noise failure between the victim line and aggressor line is computed using the timing window.Furthermore,the top-k aggressor lines which have the largest probabilities to cause false delay noise failures in real circuits can be found.The largest number of false failures can be filtered within runtime,producing a significant pessimism reduction for the crosstalk-aware timing analysis.Finally,for the more prominent physical effects in the scaled technology a statistical method for analyzing crosstalk noise with reduced distributed RC-Ï€model is proposed.Compared with other noise models,the distributed RC-Ï€model can be well suitable for long interconnects in the deep submicron process and the quiet aggressor net and tree branch reduction techniques are used to reduce the modeling complexity.Based on the reduced distributed RC-Ï€model,the local process variations in the physical dimensions of each interconnect segments are accurately extracted from the reduced model,and the crosstalk noise variable is represented as a linear canonical function of this process variations set.Then,the grid-based model is used to generate the spatial correlation among each neighboring segment of the reduced distributed RC-Ï€model,to handle both spatially correlated and independent non-Gaussian as well as Gaussian interconnect process variations. At last,the principal components analysis and independent component analysis technologies are employed to transform spatial correlated sets of Gaussian and non-Gaussian variables into sets of statistically independent variables correspondingly,and then the PDF of the crosstalk noise variable can be obtained using the moment matching scheme.Experimental results show that our method maintains the efficiency of previous approaches,and significantly improvs on their accuracy.
Keywords/Search Tags:VLSI design, Interconnection, Crosstalk noise, False noise failure, Hierarchical design, Process parameter variation
PDF Full Text Request
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